Method for fabricating a CMOS well structure

Details Method for fabricating a CMOS well structure Method for fabricating a CMOS well structure

1985-02-27

1987-05-05

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29576W, 148 15, 148187, 148DIG82, 357 42, 357 91, H01L 21263

Patent

active

046620613

ABSTRACT:
A process is disclosed for fabricating N-wells in a P-type substrate. An N-type epitaxial layer is formed on the surface of a P+ substrate. The N-type epitaxial layer is then masked and a doubly charged boron implant is performed on the exposed areas of the N-type epitaxial layer. Because of the lower mass of boron, a common production 200 kiloelectron volt implanter provides sufficient implantation energy to doubly charged boron to provide a P region which extends through the N-type epitaxial layer. The remaining N-type portions of the epitaxial layer provide N-wells for the fabrication of complementary field effect transistor circuitry.

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