System and method for addressing plurality of data values with a

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...

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712208, 711 2, 711100, G06F 1300

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active

060095083

ABSTRACT:
A computer system has instructions which have a reduction in the number of address bits relative to the number of data items that may be held during instruction execution. The instruction set comprises selectable instructions, a plurality of the instructions each including one set of bit locations identifying an operation to be carried out by execution of the instruction and a second set of bit locations to identify an address of a data storage location for use in execution of the instruction. The computer system further includes a plurality of addressable data storage locations for holding simultaneously a plurality of data values during execution of a sequence of instructions, with at least one of the data storage locations comprising a multi-value store requiring a single address in an instruction and arranged to hold a plurality of data values simultaneously on a first-in, first-out basis. This therefore increases the number of data values that can be held in relation to the number of addresses that can be identified by the second set of bit locations.
A method of executing a succession of instructions in a computer system is also described.

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Standard Search Report dated Oct. 20, 1994.
ICL Technical Journal, vol. 4, No. 3, May 1985, Hitchin GB, pp. 248-259, D.W. Ashcroft "Processing Node of the ICL Series 39 Level 30 System".
David Gries "The science of programming", 1981.

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