Patent
1990-03-19
1991-11-26
Hille, Rolf
357 54, H01L 2194, H01L 2195
Patent
active
050687115
ABSTRACT:
A semiconductor device having a multi-level interconnection structure includes an active device, a substrate supporting the active device thereon, and a first insulator layer provided so as to cover the substrate including the active device. A first conductor pattern is provided on the first insulator layer. A planarizing layer has a planarized top surface provided on the first insulator layer so as to bury the first conductor pattern underneath. A second insulator layer is provided on the planarized top surface of the planarizing layer. A contact hole is provided on the second insulator layer so as to expose a desired part of the first conductor pattern. A second conductor pattern is provided on the second insulator layer in correspondence to the contact hole so as to fill the contact hole and so as to make a contact to the exposed part of the first conductor pattern. An isolated region is provided on the substrate in correspondence to a part of the substrate underneath the contact hole such that the isolated region is projected from the first top surface of the substrate in correspondence to the contact hole. The isolated region causes a projection of the top surface of the first insulator layer in correspondence to a part which covers the isolated region such that the planarizing layer provided on the first insulator layer is eliminated from the part of the first insulator having the projecting top surface.
REFERENCES:
patent: 4485393 (1984-11-01), Kumamaru et al.
patent: 4621277 (1986-11-01), Ito et al.
patent: 4733289 (1988-03-01), Tsurumaru
patent: 4879257 (1989-11-01), Patrick
"Refractory Contact Stud", IBM Technical Disclosure, vol, 29, No. 11, Apr. 1987, pp. 5091-5092.
Planarization Process Using Spin-On-Glass, G. H. Ting et al., IEEE VLSI Multilevel Interconnection Conference, Jun. 1987.
Clark S. V.
Fujitsu Limited
Hille Rolf
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