Pipeline risc processing unit with improved efficiency when hand

Details Pipeline risc processing unit with improved efficiency when hand Pipeline risc processing unit with improved efficiency when hand

1991-12-12

1995-04-04

Bowler, Alyssa H.

Boots, shoes, and leggings

395375, 364DIG1, 36423223, 3642318, 364260, 364258, 364DIG2, 36493155, G06F 100

Patent

active

054045525

ABSTRACT:
Source operand data supplied from a register file are held in registers. The data of the registers and load data from a data memory are bypassed and supplied to a selection circuit. An execution stage includes an arithmetic and logic unit for performing an operation on the source operand data and a memory access stage includes an arithmetic and logic unit for performing an operation on data selected by the selection circuit. Selection of the selection circuit is controlled by data dependency between a load instruction and an operation instruction following the same. The output of the arithmetic and logic unit in the execution stage and the output of the arithmetic and logic unit in the memory access stage are selected in a selector according to a presence/absence of data dependency. Load data from the data memory is also supplied to the selector. If an operation instruction supplied following a load instruction uses load data, execution of this operation instruction in the memory access stage eliminates a pipeline stall and the need for inserting a "NOP" instruction for pipeline stall prevention, making it possible for an operational processing unit to operate at a high speed without causing a slot in the pipeline.

REFERENCES:
patent: 4831515 (1989-05-01), Kamada et al.
patent: 5043868 (1991-08-01), Kitamura et al.
patent: 5075849 (1991-12-01), Kuriyama et al.
patent: 5123108 (1992-06-01), Olson et al.
patent: 5222240 (1993-06-01), Patel
"MIPS-X: A 20-MIPS Peak, 32-bit Microprocessor with On-Chip Cache", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, by Mark Horowitz et al, Oct. 1980, pp. 790-797.
Kai Hwang, et al, "Computer Architecture and Parallel Processing," pp. 187-203.

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