Parallel processing apparatus and method capable of switching pa

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364DIG1, 3642287, 364229, 364230, 3642303, 3642319, G06F 9445

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active

054044723

ABSTRACT:
When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.

REFERENCES:
patent: 4942525 (1990-07-01), Shintani et al.
David T. Hilja "Reducing the Branch Penalty in Pipe-line Processors," Computer (Jul. 1988) pp. 47-55.
Miller et al. "Floating-Duplex Decode and Execution of Instructions", IBM Technical Disclosure Bulletin, vol. 23, No. 1, (Jun. 1980) pp. 409-412.

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