Digital clock frequency multiplier

Details Digital clock frequency multiplier Digital clock frequency multiplier

1998-02-27

1999-12-28

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327116, 327119, 327284, H03B 1900

Patent

active

060086769

ABSTRACT:
This invention describes a circuit and method for creating a double clock frequency. The circuit uses a sequence of delay elements to delay the primary clock. A delay detector determines when a delayed clock is out of phase with the primary clock. A delay is selected that is one half the delay producing the out of phase delayed clock. The selected delay is used to combine with the primary clock to produce a double clock frequency. Control signals for selecting the "half" delayed clock are latched to prevent clock jitter and spurious signal from producing error signals in the double frequency clock. Different duty cycles can be established by varying the selected delay.

REFERENCES:
patent: 4600895 (1986-07-01), Landsman
patent: 4799022 (1989-01-01), Skierszkan
patent: 5530387 (1996-06-01), Kim

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