Multiprocessor system and architecture with a computation system

Details Multiprocessor system and architecture with a computation system Multiprocessor system and architecture with a computation system

1993-07-15

1994-06-28

Kulik, Paul V.

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395800, 395 27, 364DIG2, 364916, 3649162, 3649642, 36496427, 3649724, G06F 1314, G06F 1200

Patent

active

053255100

ABSTRACT:
Hierarchical multiprocessors systems with common level expansion modules. The invention includes an architecture for such multiprocessor system. One facet of such multiprocessor system including a memory control system for minimizing duplicate read requests comprising: a plurality of processing systems; a bus connecting the processing systems; a memory for storing variables; circuitry operable for receiving read requests through the bus from other processing systems; a memory for queuing incoming read requests, wherein the memory for queuing incoming read requests is connected to the circuitry operable for receiving read requests; a memory for queuing outgoing read requests, wherein the memory for queuing outgoing read requests is connected to bus and the memory for storing variables; and circuitry for comparing the incoming read requests to the queued read requests, wherein the circuitry ignores duplicates of a first read request prior to the first read request leaving the memory for queuing outgoing read requests.

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Ralston, Anthony, "Encyclopedia of Computer Science," 1976, pp. 1187-1189.

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