Symmetrical multi-layer metal logic array with continuous substr

Details Symmetrical multi-layer metal logic array with continuous substr Symmetrical multi-layer metal logic array with continuous substr

1994-02-10

1995-04-04

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257204, H01L 2710

Patent

active

054040345

ABSTRACT:
A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

REFERENCES:
patent: 4651190 (1987-03-01), Suzuki et al.
patent: 4884118 (1989-11-01), Hui et al.
patent: 4999698 (1991-03-01), Okuno et al.
patent: 5072285 (1991-12-01), Ueda et al.

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