Method for simultaneous formation of contacts between metal laye

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state

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644636, 644648, H01L 2182

Patent

active

060080752

ABSTRACT:
A method for simultaneous fabrication of an interlever metal contact and a fuse window reducing the number of masking steps required while providing a high yield for the fuse. A semiconductor substrate is provided having a device area with a first metal layer over an InterLevel Dielectric layer and a fuse area with a polysilicon fuse buried within the InterLevel Dielectric layer. A thick anti-reflective coating is formed on the first metal layer. The first metal layer and the anti-reflective coating are patterned to form a first metal line. An InterMetal Dielectric layer is formed over the InterLevel Dielectric layer and the first metal line. The InterMetal Dielectric layer, the InterLevel Dielectric layer, and the anti-reflective coating are patterned, simultaneously opening a via hole extending partially into the anti-reflective coating and a fuse window opening extending into the InterLevel Dielectric layer without exposing the fuse. An adhesion layer is formed over the InterMetal Dielectric layer. A Tungsten layer is blanket deposited on the adhesion layer and anisotropically etched, forming a W-plug in the via hole and a W-ring on the sidewalls of the fuse window opening. An upper metal layer is formed on the adhesion layer, the W-plug, and the W-ring and patterned to form an upper metal line. This etch also forms an upper metal ring on the inside wall of the W-ring. A passivation layer and a dielectric layer are formed and patterned to extend the fuse window opening through the passivation layer without exposing the fuse.

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