Process for manufacturing a stacked multiple leadframe semicondu

Details Process for manufacturing a stacked multiple leadframe semicondu Process for manufacturing a stacked multiple leadframe semicondu

1993-01-29

1995-04-04

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437220, 437915, H01L 2158, H01L 2160, H01L 2152, H01L 2156

Patent

active

054037840

ABSTRACT:
A process for manufacturing a pin grid array package providing a plurality of electrical input and/or output connections using a plurality of stacked, but spaced apart, separate leadframes which are preformed and include a plurality of electrical leads having first and second ends for providing a plurality of different connections. An insulating layer is positioned between adjacent leadframes and the package is bonded together.

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