Method of manufacturing double-layer gate programmable ROM

Details Method of manufacturing double-layer gate programmable ROM Method of manufacturing double-layer gate programmable ROM

1993-09-16

1995-04-04

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 49, 437 52, 437 45, H01L 21265

Patent

active

054037654

ABSTRACT:
A method of manufacturing a double-layer gate programmable ROM is disclosed including the steps of: forming a plurality of first gate layers at predetermined intervals on a semiconductor substrate, source and drain regions being formed on the surface of the semiconductor substrate and under the first gate layers, respectively; forming a plurality of second gate layers between the first gate layers, channel regions being formed on the surface of the semiconductor substrate and under the second gate layers, respectively; and selectively implanting ions into the channel regions to program data. In particular, the second gates are formed between the first gate layers so as to provide partial vertically overlapped portions at which one end of each of the second gate layers is overlapped partially with the other end of each of the first gate layers, respectively, and the ion implantation into the channel regions is effected under such a condition that ions can penetrate the first and second layers, but cannot penetrate the overlapped portions of both the first and second layers. Transistors are first formed having a first E-type threshold voltage. Selective ion implantation lowers the threshold voltage of certain of the transistors to program the data into the ROM.

REFERENCES:
patent: 4294001 (1981-10-01), Kuo
patent: 4898840 (1990-02-01), Okuyama
patent: 5081052 (1992-01-01), Kobayashi et al.
patent: 5149664 (1992-09-01), Shin et al.
patent: 5149667 (1992-09-01), Choi

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