Fishing – trapping – and vermin destroying
Patent
1992-10-02
1995-04-04
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 41, 437 52, 437200, 257903, 257 67, 257 69, H01L 21265
Patent
active
054037590
ABSTRACT:
A method of fabricating a transistor on a wafer including; forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.
REFERENCES:
patent: 4821085 (1989-04-01), Haken et al.
patent: 4873204 (1989-10-01), Wong et al.
patent: 4889829 (1989-12-01), Kawai
patent: 5302538 (1994-04-01), Ishikawa et al.
patent: 5302539 (1994-04-01), Haken et al.
patent: 5306667 (1994-04-01), Shappir
DeLeon Ruben C.
Donaldson Richard L.
Gurley Lynne A.
Hearn Brian E.
Kesterson James C.
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