Bit addressing system

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395166, 3642551, 3642595, 364DIG1, G06F 1200, G06F 1204

Patent

active

053576209

ABSTRACT:
A bit addressing system is disclosed in which on N-bit long addressing for the main storage is executed by means of a computation including a plurality of fields in an addressing operand. When there exist predetermined fields in the addressing operand, the value determined by the fields is regarded as the value for the bit unit in the two's complement representation, and a base address and a bit offset are generated by adding the value obtained by shifting the bit unit value by M bits in the direction of the lower order bits, to the address of the byte unit. Namely, it becomes possible to designate two effective addresses of a base address which is a byte address and a bit offset which is the bit displacement from the base address by means of a single operand. The range of designation of the bit offset is from -2.sup.N-1 bit to (+2.sup.N-1 -1) bit, and it is possible to designate the range of 2.sup.N+M bits as bit addresses.

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patent: 5034900 (1991-07-01), Kimura et al.
I. Cramer, "The Z8000 family provides advanced system solutions", IEEE Electro, vol. 8, Suppl., 1983, pp. 2/1/1-2/1/9.

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