Method of fabricating an electronic interconnection

Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement

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174267, 361760, 2281801, 22818021, 439 74, 439 83, H05K 100

Patent

active

053248929

ABSTRACT:
Disclosed is a method of fabricating an electronic interconnection structure comprising at least one solder column Joined to an I/O pad of a substrate, the method including the steps of:

REFERENCES:
patent: 4545610 (1985-10-01), Lakritz et al.
patent: 4673772 (1987-06-01), Satoh et al.
patent: 4705205 (1987-11-01), Allen et al.
patent: 4724472 (1988-02-01), Sugimoto et al.
patent: 4914814 (1990-05-01), Behun et al.
Ozmar, IBM Technical Disclosure Bulletin, vol. 33, No. 2, Jul. 1990, p. 253, entitled: Thermal Fatigue-Resistant Joint for I/C Packaging Applications.

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