Programmable mode select by reset

Details Programmable mode select by reset Programmable mode select by reset

1980-09-29

1984-02-14

Chan, Eddie P.

Boots, shoes, and leggings

G06F 300, H03K 1700

Patent

active

044320493

ABSTRACT:
A mode selection circuit is disclosed which is suitable for configuring a data processor at the time at which the data processor is initialized with a reset signal. Mode selection latches are coupled to terminals normally used as an input/output port for the data processor and the latches are clocked with a signal generated by a level detector circuit which senses the reset signal. The mode selection latches are programmed by applying appropriate logic levels to the terminals of the input/output port at the time at which the data processor is being reset. The circuitry is adapted for allowing the connection of a diode from a terminal of the input/output port to the reset terminal of the data processor in order to program a low logic level into the corresponding mode detection latch.

REFERENCES:
patent: 3470538 (1969-09-01), Harbaugh
patent: 3535560 (1977-10-01), Cliff
patent: 3786433 (1974-01-01), Notley et al.
patent: 3931507 (1976-01-01), Brantingham
patent: 4030073 (1977-06-01), Armstrong, Jr.
patent: 4051326 (1977-09-01), Badagnani et al.
patent: 4089062 (1978-05-01), McElroy et al.
patent: 4097923 (1978-06-01), Eckert, Jr. et al.
patent: 4148099 (1979-04-01), Lauffer et al.

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