Parallelized difference flag logic

Details Parallelized difference flag logic Parallelized difference flag logic

1992-05-29

1994-10-18

Wambach, Margaret Rose

Communications: electrical

Digital comparator systems

307355, G06F 702

Patent

active

053572360

ABSTRACT:
Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status without the use of subtractor circuitry. Bit comparators, which determine if a first bit is less than, equal to, or greater than a second bit, of a magnitude comparator are divided into groups which generate compare output signals in parallel to one another, thereby reducing total magnitude comparator delay and resulting in faster operation. These compare output signals are the inputs of a control element which determines which compare output signal is allowed to pass through as the final compare output signal. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. In addition, control of selected bits, such as the most significant bits (MSBs), of the numbers is included and may be used as necessary to avoid a wrap-around condition.

REFERENCES:
patent: 4728927 (1988-03-01), Aman
patent: 4935719 (1990-06-01), McClure
patent: 5027330 (1991-06-01), Miller
patent: 5060143 (1991-10-01), Lee
patent: 5084841 (1992-01-01), Williams et al.
patent: 5165046 (1992-11-01), Hesson
Electronic Engineering vol. 62, No. 760, pp. 27-28 Apr. 1990, London GB.

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