Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1977-09-08
1978-12-19
Tupman, W.
Metal working
Method of mechanical manufacture
Assembling or joining
29577R, 29578, B01J 1700
Patent
active
041299361
ABSTRACT:
A method for manufacturing ROM's composed of a plurality of matrix-arranged IGFET's comprises a process for manufacturing a semiconductor device with no information yet written therein and a process for completing the ROM by writing predetermined information or memory in the no-information semiconductor device according to orders from users. The no-information semiconductor device may be produced by first forming a plurality of relatively thick rectangular oxide layers with a predetermined length, for separating the IGFET's, in parallel with one another on a substrate, then covering the whole surface of the substrate with a gate oxide layer and forming on such gate oxide layer a plurality of selective lines composed of polycrystalline silicon extending in parallel with one another across the separating oxide layers, removing the gate oxide film in regions surrounded by the selective lines and the separating oxide layers, and finally diffusing an impurity in the substrate by the thermal diffusion method to form a plurality of strip-shaped source regions and square drain regions. In storing memory in such no-information semiconductor device to complete the ROM, the whole surface of the semiconductor device, except specified gate regions between the source and drain regions corresponding to specified IGFET's, is covered with a photo-resist film, and the substrate is implanted with an impurity with the same type of conductivity as that of such substrate through the gate and gate oxide layer by the ion implantation method. Thereafter, the photo-resist film is removed, an oxide layer is grown over the surface by the low-temperature growth method, contact holes are bored through the oxide layer on the drain regions, and data lines composed of a plurality of parallel aluminum films substantially at regular intervals are formed on such oxide layer, the data lines passing over the contact holes across the selective lines. Portions of the substrate under the gates of specified IGFET's have a higher impurity concentration as compared with portions under the gates of other IGFET's, and the threshold voltage at the gates of such specified IFGET's is higher than that of other IGFET's.
REFERENCES:
patent: 3865651 (1975-02-01), Arita
patent: 3996657 (1976-12-01), Simko
patent: 4050965 (1977-09-01), Ipri
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