Interrupt cascading and priority configuration for a symmetrical

Details Interrupt cascading and priority configuration for a symmetrical Interrupt cascading and priority configuration for a symmetrical

1994-05-31

1996-10-22

Coleman, Eric

Boots, shoes, and leggings

3642302, 364230, 3642604, 364DIG1, G06F 1324

Patent

active

055686494

ABSTRACT:
A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions. An auto-chaining technique is further implemented by the central interrupt control unit to sequentially provide broadcast interrupts to various processing units based on their current task priority values. Finally, the central interrupt control unit further handles system management interrupts (SMIs) from sources such as power management units and ensures proper system operation even if the requested system management function affects operations being carried by other processing units.

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Intel, "MultiProcessor Specification", Version 1.1 (Apr. 1994).

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