Method for rearranging instruction sequence in risc architecture

Details Method for rearranging instruction sequence in risc architecture Method for rearranging instruction sequence in risc architecture

1995-02-13

1996-10-22

Lim, Krisna

Boots, shoes, and leggings

395600, 395700, 395800, 364DIGI, 364DIGII, G06F 945

Patent

active

055686230

ABSTRACT:
In order to improve the efficiency with which a given set of instructions can be implemented in a RISC architecture environment, the set of instructions are subject to a plurality of requirements and the sequences of instructions which satisfy the requirements are listed. The most time efficient of the listed sequences is selected.

REFERENCES:
patent: 4486830 (1984-12-01), Taylor et al.
patent: 4789925 (1988-12-01), Lahti
patent: 4814976 (1989-03-01), Hansen et al.
patent: 4831515 (1989-05-01), Kamada et al.
patent: 4891754 (1990-01-01), Boreland
patent: 5185868 (1993-02-01), Tran
patent: 5185871 (1993-02-01), Frey et al.
patent: 5303377 (1994-04-01), Gupta et al.
The i960CA SuperScalar Implementation of the 80960 Architecture IEEE 1990 (S. McGeady).
A 32-Bit RISC processor Board for a frequency Hopping Radio. IEEE 1990 (T.S.D. Tsui et al.).

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