Cache memory system with independently accessible subdivided cac

Details Cache memory system with independently accessible subdivided cac Cache memory system with independently accessible subdivided cac

1996-02-21

1997-10-07

Chan, Eddie P.

395455, 395463, 395471, 395494, 395495, G06F 1208, G06F 1316

Patent

active

056757654

ABSTRACT:
Two independently accessible subdivided cache tag arrays and a cache control logic is provided to a set associative cache system. Each tag entry is stored in two subdivided cache tag arrays, a physical and a set tag array such that each physical tag array entry has a corresponding set tag array entry. Each physical tag array entry stores the tag addresses and control bits for a set of cache lines. The control bits comprise at least one validity bit indicating whether the data stored in the corresponding cache line is valid. Each set tag array entry stores the descriptive bits for a set of cache lines which consists of the most recently used (MRU) field identifying the most recently used cache lines of the cache set. Each subdivided tag array is provided with its own interface to enable each array to be accessed concurrently but independently by the cache control logic which performs read and write operations against the cache. The cache control logic makes concurrent and independent accesses to the separate tag arrays to read and write the control and descriptive information in the tag entries. The accesses are grouped by type of operation to be performed and each type of accesses is made during predesignated time slots in an optimized manner to enable the cache control logic to perform certain selected read/write accesses to the physical tag array while performing other selected independent read/write accesses to the set tag array concurrently.

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The Cache Memory Handbook; Jim Handy; Academic Press, Inc.; 1993; pp. 132-133.

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