Dual path switch gate array

Details Dual path switch gate array Dual path switch gate array

1987-11-10

1989-07-25

Atkinson, Charles E.

Excavating

G01R 3128

Patent

active

048520942

ABSTRACT:
A dual path switch (DPS) circuit for interfacing between arithmetic elements of a computer for performing Fast Fourier Transforms. The ratio of power consumption to signal resolution is very low. The DPS has very high frequency resolution, and to conserve power, many of its registers are reset to a logic low status when they are not in use. The DPS includes a diagnostic system which, upon a hardware failure, identifies the faulty gate and specifies the nature of the fault. The diagnostic system also provides a fault signal for use in testing for the mean time between failures.

REFERENCES:
patent: 3633016 (1972-01-01), Walker et al.
patent: 3961252 (1976-06-01), Eichelberger
patent: 4667330 (1987-05-01), Kumagai
patent: 4750181 (1988-06-01), McDonald et al.
Sellers, Jr. et al., Error Detecting Logic for Digital Computers, McGraw-Hill Book Co., New York, 1968, pp. 254-255.

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