Semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

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365182, 36523006, G11C 1140, G11C 1300

Patent

active

048520667

ABSTRACT:
A semiconductor memory device includes a column decoder which is constructed such that it selects two adjacent columns in a memory cell array, and by means of which one of the two columns at a higher or lower position is selected, depending on whether or not a control signal indicates that one is added to a designated address. When the designated column address is the most significant address, the most and least significant addresses are selected, and if, in this case, the control signal indicates that one is added to the designated address, the least significant column address is selected and an address carry signal is generated. If, on the other hand, the control signal indicates that one is not added to the designated address, then the most significant column address is selected, in which case no address carry signal is generated. Similarly, a row decoder is constructed such that it selects two adjacent rows in the memory cell array, and one of the two columns at a higher or lower position is respectively selected, depending on whether or not an address carry signal is generated from the column decoder. When the designated row address is the most significant address, the most and least significant addresses are selected, and if, in this case, the address carry signal is generated from the column decoder, the least significant row address is selected, while if the address carry signal is not generated, then the most significant row address is selected.

REFERENCES:
patent: 4763304 (1988-08-01), Uesugi
Ochii et al., "A 17ns 64K CMOS RAM with a Schmitt Trigger Sense Amplifier," ISSCC Digest of Technical Papers, pp. 64-65, Feb. 13, 1985.
Saito et al., "A 1Mb CMOS DRAM with Fast Page and Static Column Modes," ISSCC Digest of Technical Papers, pp. 252-253, Feb. 15, 1985.

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