Programmable variable-cycle clock circuit for skew-tolerant arra

Details Programmable variable-cycle clock circuit for skew-tolerant arra Programmable variable-cycle clock circuit for skew-tolerant arra

1987-06-19

1989-07-25

Williams, Jr., Archie E.

Boots, shoes, and leggings

364228, 3642318, 36423222, 364270, 3642702, 3642705, 3642707, 364271, 3642712, G06F 500, G06F 504, G06F 506, G06F 938

Patent

active

048519952

ABSTRACT:
Using a variable-duration clock circuit, together with programmable duration control to alter the clock waveform within strict rules, permits the programmer to arrange appropriately short durations for short data transfers, and to arrange appropriately longer durations for longer data transfers in an array processor of myriad processing elements. There is no need to allow sufficient time in every clock cycle for worst case data transfer between remote processing elements.
The clock waveform has three recognizable edges (A,B,C) regardless of loss of sharpness during its travel to the various processing elements. The convention that three skew-sensitive activities, READ, WRITE and OPERAND SUPPLY conform to respectively assigned edges as follows:

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