Process for production of integrated MOS circuits with and witho

Details Process for production of integrated MOS circuits with and witho Process for production of integrated MOS circuits with and witho

1980-05-29

1981-12-22

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 148 15, 148187, 357 23, H01L 2126

Patent

active

043063535

ABSTRACT:
Integrated MOS circuits with and without MNOS memory transistors in silicon-gate technology are produced with overlapped contacts using a silicon nitride mask. After production of structured SiO.sub.2 layers on a p- or n- doped semiconductor substrate to separate active transistor zones in accordance with the so-called LOCOS process, a silicon nitride layer is deposited onto the surface and is then structured so that the zones in which a gate oxide is to be produced, are uncovered and during gate oxidation, the surface of this structured silicon nitride layer is converted into an oxynitride layer. In contrast to previously known processes, the invention provides self-aligned overlapped contacts with oversized contact holes. The silicon-nitride layer functions as an etch-stop during etching of an intermediate oxide. This avoids under-etching of the polysilicon during contact hole etching. The overlapped contacts allow a substantial increase in the packing and integration density of the so-produced circuits.

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Oldham et al., "Improved Integrated Circuit Contact Geometry Using Local Oxidation," Proceedings of Electrochem. Soc., Abst. 277, May 1978, pp. 690-691.
Rideout et al., "A One-Device Memory Cell Using a Single Layer of Polysilicon and a Self-Registering Metal-To-Polysilicon Contact, 38 Int. Electron Devices Meeting, _Technical Digest, Wash. D.C., Dec. 1977, pp. 258-261.

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