Internally register-modelled, serially-bussed radio system

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34082507, 455 31, 379 63, G06F 1110, H04B 700

Patent

active

046370226

ABSTRACT:
In accordance with the present invention, there is provided a register-modelled radio system comprising a plurality of register-modelled processors having addressable registers for modelling the virtual state of the processor; a serial bus, interconnecting the register-modelled processors for communicating between the addressable registers; and a communications protocol for passing information to or from the addressable registers, whereby the virtual state of a radio portion may be determined or altered by, respectively, communicating information from or to the addressable registers. The communications protocol further comprises an information packet having an address, an operation code, optional data, and an error detection device, such as a cyclical redundancy check packet. The operation code is chosed from the group of primitive operation codes reset, read, write, bit set, bit clear, acknowledge, and negative acknowledge.

REFERENCES:
patent: 4352955 (1982-10-01), Kai et al.
patent: 4414661 (1983-11-01), Karlstrom
patent: 4430755 (1984-02-01), Nadir et al.
patent: 4481670 (1984-11-01), Freeburg
patent: 4486624 (1984-12-01), Puhl et al.
patent: 4590473 (1986-05-01), Burke et al.
patent: 4594591 (1986-06-01), Burke

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