Summation of address transition signals

Details Summation of address transition signals Summation of address transition signals

1985-08-16

1987-01-13

Popek, Joseph A.

Static information storage and retrieval

Addressing

365203, G11C 800

Patent

active

046369910

ABSTRACT:
A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address.

REFERENCES:
patent: 4272832 (1981-06-01), Ito
patent: 4355377 (1982-10-01), Sud et al.
patent: 4581718 (1986-04-01), Oishi

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