Vernier addressing apparatus

Details Vernier addressing apparatus Vernier addressing apparatus

1982-07-21

1987-01-13

Thomas, James D.

Boots, shoes, and leggings

364900, G06F 752

Patent

active

046369732

ABSTRACT:
A vernier address scale reduces the number of addressable memory locations required for numerical look-up tables. Read-only memories (ROMs) store the data of linear or non-linear functions. Decoders determine which ROM is selected and advantage is taken of accuracy improvement as numbers become large by dropping least significant bits as the vernier address scale moves from one ROM table to another. Accuracy is further improved by using a method of one-half level quantization step for rounding. This reduces the size of numerical tables for math processing of reciprocals, roots of numbers, powers of numbers, logarithms, trigonometric and exponential functions.

REFERENCES:
patent: 3328767 (1967-06-01), Ottaway
patent: 3610905 (1971-10-01), Herron et al.
patent: 3648038 (1972-03-01), Sierra
patent: 3735110 (1973-05-01), LeComte
patent: 3809868 (1974-05-01), Villalobos et al.
patent: 3917935 (1975-11-01), Lazecki
patent: 4150364 (1979-04-01), Baltzer
patent: 4276607 (1981-06-01), Wong
patent: 4313174 (1982-01-01), White
patent: 4357674 (1982-11-01), Ikeda et al.
patent: 4374427 (1983-02-01), Katayama
patent: 4470125 (1984-09-01), Dischert et al.

Affiliated with

Also associated with

Rating

Vernier addressing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vernier addressing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vernier addressing apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2360871