Error correcting circuits and methods for shift register type me

Registers – Systems controlled by data bearing records – Time analysis

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365 77, G11C 2900

Patent

active

040888762

ABSTRACT:
This disclosure relates to error correcting circuits and methods employed thereby for shift register type memories which are formed of a plurality of loops that may be accessed in parallel. Such circuitry is designed to detect when the output of a given loop or shift register becomes a series of ones or a series of zeros which conditions indicate burst mode error. The data bit corresponding to the loop or shift register producing the error is then corrected by complementation.

REFERENCES:
patent: 3792450 (1974-02-01), Bogar et al.
patent: 3794819 (1974-02-01), Berding
patent: 4024509 (1977-05-01), Elmer
patent: 4028539 (1977-06-01), Jacobs

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