Method of fabricating gate electrode of CMOS device

Details Method of fabricating gate electrode of CMOS device Method of fabricating gate electrode of CMOS device

1995-11-06

1996-10-22

Fourson, George

Fishing, trapping, and vermin destroying

437 34, 437 56, 437 58, 437186, 437200, 148DIG19, 257369, 257371, H01L 2170

Patent

active

055676421

ABSTRACT:
A method of fabricating a gate electrode of a CMOS device is disclosed including the steps of: sequentially forming a gate insulating layer, first conductive layer and protective layer on a semiconductor substrate; selectively etching a predetermined portion of the protective layer in which a PMOS transistor will be formed; forming a second conductive layer on the overall surface of said substrate; removing the second conductive layer formed on the protective layer, and partially etching the protective layer to a predetermined thickness; and patterning the second conductive layer, the protective layer, the first conductive layer and the gate insulating layer using a gate electrode pattern.

REFERENCES:
patent: 4635347 (1987-01-01), Lien et al.
patent: 5449637 (1995-09-01), Saito et al.
patent: 5480830 (1996-01-01), Liao et al.

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