Process for the production of a memory cell

Details Process for the production of a memory cell Process for the production of a memory cell

1988-07-08

1989-07-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 41, 437 44, 437 48, 437 50, 437 51, 437190, 437191, 437193, 437228, H01L 2122

Patent

active

048513652

ABSTRACT:
A process for producing a memory cell, particularly of the ROM or EPROM type, having a matrix of memory points, each memory point comprising a source, a drain and at least one gate. In a first step, a mask is produced for defining the position of stacks in which the gates are produced. This is followed by the production of the sources and the drains during second and third successive and independent steps. The second step consists of an etching operation, a doping operation and an insulating operation, while the third step involves an etching operation and a doping operation. The operation is completed by producing the conductive lines connecting the drains of the memory points aligned in a direction Y.

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patent: 4493057 (1985-01-01), McElroy
patent: 4597827 (1986-07-01), Nishitami et al.
patent: 4645563 (1987-02-01), Terada et al.
IBM Technical Disclosure Bulletin (vol. 29, No. 3, Aug. 1986, p. 1328).
IBM Technical Disclosure Bulletin (vol. 26, No. 9, Feb. 1984, pp. 4587-4589).

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