Ratioless FET programmable logic array

Details Ratioless FET programmable logic array Ratioless FET programmable logic array

1984-12-21

1987-01-13

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307482, 307594, 307481, H03K 19177, H03K 19094, H03K 19003

Patent

active

046366610

ABSTRACT:
A ratioless, zero d.c. power dissipating FET programmable logic array including a column boost capacitor for maintaining the columns of selected AND array transistors at approximately their precharged voltage while their associated OR array transistors are being evaluated.

REFERENCES:
patent: 3943377 (1976-03-01), Suzuki
patent: 4040015 (1977-08-01), Fukuda
patent: 4291247 (1981-09-01), Cooper, Jr. et al.
patent: 4295064 (1981-10-01), Schuster
patent: 4501977 (1985-02-01), Koike
Wood, "High-Speed Dynamic Programmable Logic Array Chip"; IBM J. Res. Develop.; 7/1975; pp. 379-383.

Affiliated with

Also associated with

Rating

Ratioless FET programmable logic array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ratioless FET programmable logic array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ratioless FET programmable logic array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2357275