High speed parity prediction for binary adders using irregular g

Details High speed parity prediction for binary adders using irregular g High speed parity prediction for binary adders using irregular g

1988-04-25

1990-05-08

Smith, Jerry

Boots, shoes, and leggings

371 494, G06F 1110

Patent

active

049244230

ABSTRACT:
Parity for every byte of the sum produced by addition of two operands is predicted based upon segmentation of each sum byte into three irregular groups of adjacent bits. Parity is generated for each group and the group parities are combined to form the parity of the sum byte. Adder technology is used to generate the group parities from operands and carry bits, which leads to Boolean minterm circuitry employing a minimum of exclusive-OR gates.

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IBM Technical Disclosure Bulletin, vol. 23, No. 12, May 1981, Parity Predict of a Sum--P. Kalandra and A. Weinberger.
IBM Technical Disclosure Bulletin, vol. 22, No. 4, Sep. 1979, Parity Prediction for Fast Three-Input Adder, K. E. Olin and A. Weinberger.
IBM Technical Disclosure Bulletin, vol. 30, No. 3, Aug. 1987, Minimized Parity Predict Circuit for Incrementation.

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