Fishing – trapping – and vermin destroying
Patent
1995-05-02
1996-01-02
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 44, 437979, H01L 218247
Patent
active
054808219
ABSTRACT:
A virtual ground flash EEPROM array is based on a source-coupling, split-gate storage cell. The array includes a plurality of spaced-apart, parallel buried n+ bit lines formed in a P-type silicon substrate to define alternating source and drain lines that are segment-contacted. Field oxide islands formed in the array between adjacent source and drain lines define the substrate channel regions of the individual storage cell transistors. The poly1 floating gate of each cell is formed over a first portion of the substrate channel region and is separated from the channel region by a layer of floating gate oxide. Each floating gate includes a tunnelling arm that extends over the cell's source line and is separated therefrom by thin tunnel oxide. A poly2 word line is formed over the floating gates of the storage cells in each row of the array. The poly2 word line is separated from the underlying floating gate by a layer of oxide
itride/oxide (ONO). The word lines run perpendicular to the buried n+ bit lines and extend over a second portion of the channel region of each cell in the row to define the internal access transistor of the cell. The word line is separated from the second portion of the channel region by the ONO layer.
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Chaudhari Chandra
National Semiconductor Corporation
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