Scrambling/descrambling circuit

Details Scrambling/descrambling circuit Scrambling/descrambling circuit

1991-12-04

1993-07-27

Barron, Jr., Gilberto

Cryptography

Particular algorithmic function encoding

380 42, 380 46, 380 49, H04L 926, H04L 928

Patent

active

052316670

ABSTRACT:
A scrambling/descrambling circuit that may be manufactured as a CMOS arrangement in LSI format and free of constraints on the degree of the generating polynomial involved. Scrambled (or descrambled) "m" bits of data output by registers are multiplied by multiplication circuits by a factor of the generating element .alpha..sup.m of the generating polynomial. The multiplied data are input back to the registers. The scrambled "m" bits of data are supplied to "m" exclusive-OR gates for exclusive-OR operation with input data.

REFERENCES:
patent: 3784743 (1974-01-01), Schroeder
patent: 4165444 (1979-08-01), Gordon
patent: 4797921 (1989-01-01), Shiraishi
patent: 4815130 (1989-03-01), Lee et al.
patent: 4965881 (1990-10-01), Dilley et al.
"IEEE Transaction on Computers", vol. 39, No. 2, Feb. 1990, pp. 258-262 (Wang et al.).
"Electronik", vol. 32, No. 26, Dec. 1983, pp. 67-70, (Hermes et al.).
"NTZ", vol. 45, No. 5, May 1988, pp. 270-275 (Hahan et al.).

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