Multi-threaded bus master

Details Multi-threaded bus master Multi-threaded bus master

1996-06-05

2000-04-18

Sheikh, Ayaz R.

395306, 395729, 395732, G06F 1314

Patent

active

060525134

ABSTRACT:
Access to bus devices on a bus is granted in a computer system, with each bus device asserting a request signal to request the bus. A detector determines if a bus device is multi-threaded or single-threaded. An arbiter masks or does not mask the request signal of a retried bus device based on whether the bus device is a multi-threaded device. The arbiter masks the request signal of a retried bus device if it is a single-threaded device, but does not mask the request signal if the retried bus device is a multi-threaded device. The bus device request includes a delayed request transaction, and the bus includes a PCI bus.

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