Method for fabricating an interconnection pattern on a BPSG-fill

Details Method for fabricating an interconnection pattern on a BPSG-fill Method for fabricating an interconnection pattern on a BPSG-fill

1992-05-07

1993-07-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437228, 437240, 437 63, 437 64, 148DIG50, H01L 2176

Patent

active

052310469

ABSTRACT:
A semiconductor device is provided with an isolation region for isolating the semiconductor device from an adjacent semiconductor device provided commonly on a semiconductor substrate. The isolation region includes a groove extending to a predetermined depth of the substrate, a non-doped silicon oxide layer provided on a whole inner surface of the groove, and a BPSG (boro-phosho-silicate glass) layer filled in a remaining portion of the groove covered with the non-doped silicon oxide layer on the inner surface. An interconnection layer is provided on the isolating region selectively.

REFERENCES:
patent: 4571819 (1986-02-01), Rogers et al.
patent: 4740480 (1988-04-01), Ooka

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