Bit stack wiring channel optimization with fixed macro placement

Details Bit stack wiring channel optimization with fixed macro placement Bit stack wiring channel optimization with fixed macro placement

1995-02-10

1996-08-20

Teska, Kevin J.

Boots, shoes, and leggings

364490, 364491, 364489, 437 48, 437 51, 257409, 257355, 395800, G06F 1500

Patent

active

055487475

ABSTRACT:
Wiring channel assignment in very large scale integrated (VLSI) bit stack macros is optimized for fixed macro placement and variable pin placement. Nets are first prioritized by length with the longest nets having highest priority. Nets are then routed between the appropriate macros according to their priority. Pin rails or position are assigned dynamically, rather than being predetermined, as the nets are being placed with a preference towards the nearest edge of the macro, in order to minimize net length and maximize sharing of wiring channels among multiple nets.

REFERENCES:
patent: 4295149 (1981-10-01), Balyoz et al.
patent: 4593351 (1986-06-01), Hong et al.
patent: 4593362 (1986-06-01), Bergeron et al.
patent: 4607339 (1986-08-01), Davis
patent: 4890238 (1989-12-01), Klein et al.
patent: 4896272 (1990-07-01), Kurosawa
patent: 4988636 (1991-01-01), Masleid et al.
patent: 5036473 (1991-01-01), Butts et al.
patent: 5045913 (1991-09-01), Masleid et al.
patent: 5051994 (1991-09-01), Bluethman et al.
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5224057 (1993-06-01), Igarashi et al.
patent: 5225991 (1993-07-01), Dougherty
patent: 5237514 (1993-08-01), Curtin
patent: 5266912 (1993-11-01), Kledzik
patent: 5303161 (1994-04-01), Burns et al.
patent: 5308798 (1994-05-01), Brasen et al.
patent: 5309370 (1994-05-01), Wong
patent: 5353234 (1994-10-01), Takigami
patent: 5353235 (1994-10-01), Do et al.
patent: 5363313 (1994-11-01), Lee
patent: 5367469 (1994-11-01), Hartoog
patent: 5404313 (1995-04-01), Shiohara et al.
IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan. 1988, Cagle et al., pp. 303-309 "Traffic Evaluation for Dataflow Stacks in VLSI Chip Design".

Affiliated with

Also associated with

Rating

Bit stack wiring channel optimization with fixed macro placement does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bit stack wiring channel optimization with fixed macro placement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit stack wiring channel optimization with fixed macro placement will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2337695