Non-integer multiple clock translator

Details Non-integer multiple clock translator Non-integer multiple clock translator

1995-03-30

1997-05-27

Heckler, Thomas M.

G06F 112

Patent

active

056341164

ABSTRACT:
A multiple clock translator for a microprocessor is provided for synchronizing data from an external clock speed to an internal clock speed that is a non-integer multiple of the external clock speed. The translator comprises a latch circuit and a synchronization signal generator. The latch circuit receives data at the external clock speed and outputs data at the internal clock speed. The latch circuit includes an input latch and a sync latch, and receives an external clock having an enabling phase and an internal clock having an enabling phase. The input latch is docked by the enabling phase of the external clock, and the sync latch is docked by the enabling phase of the internal clock and enabled by a sync pulse. The synchronization signal generator generates a series of sync pulses that are output to the latch circuit in a selected pattern, wherein the pattern is a function of the non-integer multiple.

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E.N. Hayes, et al. "Synchronization of LSSD System Clocks to Asynchronous Signals", IBM Technical Disclosure Bulletin, vol. 27, No. 8, Jan. 1985, pp. 4934-4936.

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