Patent
1994-10-13
1997-05-27
Chan, Eddie P.
395481, 39542106, G06F 1216
Patent
active
056340389
ABSTRACT:
A common memory protection system in an apparatus having a multiprocessor configuration in which a plurality of CPUs are connected to a common RAM via a common bus, the system has a flag control section for outputting two semaphore-flag signals showing each semaphore-flag condition when the CPU checks two semaphore-flags by accessing the corresponding two semaphore-flag addresses that have complementary address values to each other, and a memory control section that allows the CPU to access any address in the common RAM via the common bus when receiving the semaphore-flag signals, both of which indicate that access to the common RAM is enabled, from the flag control section.
REFERENCES:
patent: 3576982 (1971-05-01), Duke
patent: 4597084 (1986-06-01), Dynneson et al.
patent: 4975870 (1990-12-01), Knicely et al.
Chan Eddie P.
Ellis Kevin L.
Fujitsu Limited
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