ECL latch circuit insensitive to alpha ray disturbances

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307200A, 307443, 307278, 307308, 307455, H03K 301, H03K 19086

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active

047556935

ABSTRACT:
A latch circuit inputting and holding a write data including a data input terminal for receiving a write data signal and a feedback input terminal for receiving a feedback signal from an output terminal, the latch circuit through a feedback loop, wherein the output terminal of the latch circuit outputs the write data signal at a suitable timing. The latch circuit is operated such that a potential difference between a peak voltage of a logic amplitude and a reference voltage at the side at which the feedback signal is applied is set larger than a potential difference between the peak voltage of the logic amplitude and the reference voltage at the side at which the write data signal is applied.

REFERENCES:
patent: 4506165 (1985-03-01), Gulati et al.
patent: 4540900 (1985-09-01), Early et al.
Patent Abstracts of Japan, vol. 4, No. 130, 12th Sep. 1980, p. 114 E 25; and JP-A-55-83333 (Takeda Riken Kogyo K.K.) 23-06-1980.
IBM Technical Disclosure Bulletin, vol. 24, No. 12, May 1982, New York, U.S.A.; D. B. Eardley, "Latch Circuit Insensitive to Disturb by Alpha Particles", pp. 6461-6462.

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