Method for arranging modules in an integrated circuit

Details Method for arranging modules in an integrated circuit Method for arranging modules in an integrated circuit

1989-01-13

1993-04-27

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

052068153

ABSTRACT:
A method for generating a layout of a rectangular block of cells for use with other rectangular blocks of cells in an integrated circuit. In the preferred embodiment, the method includes the steps of providing a set of component circuit cells, each of the cells being of generally rectangular shape with predefined dimensions and, then, concatenating the component cells with at least one expandable cell space between non-abutting adjacent edges of at least two of the elements such that the boundary of the concatenated set defines a block of cells having a generally rectangular shape which is coterminous with a second, predefined generally rectangular block of cells.

REFERENCES:
patent: 4686629 (1987-08-01), Noto et al.
patent: 4777606 (1988-10-01), Fournier
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 4858143 (1989-08-01), Fournier
patent: 4931946 (1990-06-01), Ravindra et al.
"A dense Gate Matrix Layout Method for MOS VLSI" by A. D. Lopez et al., IEEE trans Electron Devices, vol. ED-27, pp. 1671-1675, Aug. 1980.

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