Low noise 3V/5V CMOS bias circuit

Details Low noise 3V/5V CMOS bias circuit Low noise 3V/5V CMOS bias circuit

1996-04-19

1998-01-06

Wong, Peter S.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

327538, G05F 316, H02J 104

Patent

active

057059217

ABSTRACT:
The present invention concerns a circuit for implementing a low noise bias circuit that operates at 3 volts, 5 volts or any desired power supply voltage while avoiding production reconfiguration or post-production configuration. The present invention is implemented by using a current source designed to provide a constant current under differing conditions (e.g., such as a variation in temperature, a variation in power supply, or conditions encountered in a fast transistor process). The present circuit provides a means to adapt to varying conditions. The present circuit generally provides two bias signals that are typically used in a pre-driver circuit implementing NMOS and PMOS transistors.

REFERENCES:
patent: 4638134 (1987-01-01), Kimura
patent: 4723108 (1988-02-01), Murphy et al.
patent: 4859928 (1989-08-01), Etheridge
patent: 4883976 (1989-11-01), Deane
patent: 4978905 (1990-12-01), Hoff et al.
patent: 5045773 (1991-09-01), Westwick et al.
patent: 5179297 (1993-01-01), Hsueh et al.
patent: 5216380 (1993-06-01), Carbou
patent: 5296801 (1994-03-01), Ohtsuka et al.
patent: 5334948 (1994-08-01), Fong et al.
patent: 5578964 (1996-11-01), Kim et al.

Affiliated with

Also associated with

Rating

Low noise 3V/5V CMOS bias circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low noise 3V/5V CMOS bias circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low noise 3V/5V CMOS bias circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2332347