Charge-controlled integrating successive-approximation analog-to

Details Charge-controlled integrating successive-approximation analog-to Charge-controlled integrating successive-approximation analog-to

1991-09-05

1993-04-27

Gaffin, Jeffrey A.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341155, H03M 138

Patent

active

052066509

ABSTRACT:
A charge-controlled integrating successive-approximation analog-to-digital converter first stores a charge proportional to an unknown voltage in a manner similar to a dual-slope integrating ADC, and thereafter a successive-approximation binary search sequence algorithm is applied to the integrator to determine digital bits representative of the unknown voltage. The result is a relatively simple and inexpensive ADC having high resolution and accuracy, and comparatively fast conversion rates, and exhibiting low power consumption, high noise rejection, and multiple-speed versatility. The preferred embodiment described is a 16-bit ADC with less than 20 millisecond conversion time.

REFERENCES:
patent: 3631467 (1971-12-01), Vojvodich et al.
patent: 4195282 (1980-03-01), Cameron
patent: 4939520 (1990-07-01), Biglow
patent: 5012247 (1991-04-01), Dillman
Hermann Schmid, "An Electronic Design practical guide to A/D conversion," Electronic Design, vol. 16, No. 25, Dec. 5, 1968, pp. 50-72.

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