Method of elimination of junction punchthrough leakage via burie

Details Method of elimination of junction punchthrough leakage via burie Method of elimination of junction punchthrough leakage via burie

1994-11-23

1996-08-20

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 29, 437 40, 437913, 437 38, H01L 2144, H01L 2148

Patent

active

055479030

ABSTRACT:
A method for forming MOSFET devices, with reduced exposure to source and drain leakage currents due to punchthrough phenomena, has been developed. The structure is fabricated using a buried insulator sidewall to isolate the source and drain regions. This in turn is accomplished by creating a trench in the substrate, between the source and drain regions, and forming an insulator sidewall on the sides of the trench. A selective epitaxial process is used to refill the trench and a gate oxide is grown from the epitaxial silicon. Conventional processing completes this buried insulator MOSFET structure.

REFERENCES:
patent: 4983535 (1991-01-01), Blauchard
patent: 5108937 (1992-04-01), Tsai et al.
patent: 5270257 (1993-12-01), Shin
patent: 5380670 (1995-01-01), Hagino

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