Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1990-05-01
1993-04-27
Wojciechowicz, Edward J.
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257547, 257550, 257511, 257655, H01L 2906
Patent
active
052065359
ABSTRACT:
A semiconductor device composed of a substrate provided with a groove filled with insulating material to define an element isolating region. The groove corners are rounded and the substrate contains impurity material below the groove and in a region adjacent the groove. The impurity material is introduced to have essentially the same impurity density profile below the bottom of the groove and below the substrate surface in the region adjacent the groove.
The device may additionally be provided, if the region below and adjacent the groove is of P-type conductivity, with a buried P-type layer which opposes penetration of .alpha. particle radiation into the substrate.
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patent: 4910575 (1990-03-01), Komeda et al.
patent: 4933736 (1990-06-01), Conner et al.
"Application of a Two-Layer Planarization Process to VLSI Intermetal Dielectric and Trench Isolation Processes", IEEE Transactions on Semiconductor Manufacturing, D. J. Sheldon, et al., vol. 1, No. 4, Nov. 1988, pp. 140-146.
"The Oxidation of Shaped Silicon Surfaces", Journal of Electrochemical Society, R. B. Marcus, et al., vol. 129, No. 6, Jun. 1982, pp. 1278-1282.
"Two-Dimensional Silicon Oxidation Experiments and Theory", International Electron Devices Meeting, Dah Bin Kao, et al., Dec. 1985, pp. 388-391.
Seiko Epson Corporation
Wojciechowicz Edward J.
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