Buffer store including control apparatus which facilitates the c

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G06F 1300

Patent

active

041569067

ABSTRACT:
A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a store having a plurality of word locations arranged into a number of groups or sets of blocks of word locations, a data directory for storing addresses within a plurality of locations corresponding in number to the number of groups and a control directory including a plurality of multibit locations corresponding in number to the number of groups of blocks. The cache unit further includes an input command buffer for storing commands received by the data processing unit and control logic circuits. The control logic circuits include decoder circuits operative to set to a predetermined state the contents of a predetermined bit of the control directory multibit locations identified by the memory command when the data directory indicates that the information does not reside in the cache unit store. The control logic circuits include circuits for forwarding the command to main store. In response to each subsequentread command generated by the data processing unit, the control and data directories are accessed and upon detecting that the predetermined bit of a control directory multibit location associated with the block specified by such command, the control logic circuits generate signals to inhibit the processing unit from performing further operations and the cache unit from transferring a duplicate command to the main store.

REFERENCES:
patent: 3588839 (1971-06-01), Belady et al.
patent: 3611315 (1971-10-01), Muano et al.
patent: 3693165 (1972-09-01), Reiley et al.
patent: 3699533 (1972-10-01), Hunter
patent: 3786427 (1974-01-01), Schmidt et al.

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