Method of manufacturing a semiconductor memory device having a c

Details Method of manufacturing a semiconductor memory device having a c Method of manufacturing a semiconductor memory device having a c

1995-10-25

1997-05-27

Tsai, Jey

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438398, H01L 2170, H01L 2700

Patent

active

056331886

ABSTRACT:
A method of manufacturing a semiconductor device includes forming a first insulating layer on a major surface of a semiconductor substrate. The first insulating layer has an opening located at a predetermined position on and reaching the major surface of the substrate. A first conductive layer is formed in the opening and in contact with the surface of the first insulating layer. A second insulating layer is formed on a predetermined region of the first conductive layer. A second conductive layer is formed to cover at least the second insulating layer. The second conductive layer is removed from at least an upper surface of the second insulating layer to expose the upper surface thereof. The exposed upper surface of the second insulating layer is etched to partially remove a predetermined thickness of the second insulating layer. The second conductive layer is sputter-etched with inert gas to substantially round the tip and flatten a side surface thereof. A capacitor insulating layer is formed to cover the second conductive layer after removing the residual second insulating layer. A third conductive layer is formed to cover the capacitor insulating layer. The sputter-etching of the second conductive layer results in a side surface roughness of the second conductive layer of no more than 200 .ANG..

REFERENCES:
patent: 5023683 (1991-06-01), Yamada
patent: 5381029 (1995-01-01), Eguchi et al.
patent: 5480826 (1996-01-01), Sugahara et al.
"Glow Discharge Processes", by Brian Chapman, A Wiley-Interscience Publication, 1980, pp. 247-248.
"A Novel Stacked Capacitor Cell With Dual Cell Plate for 64Mb DRAMs", by H. Arima et al., IEEE 1990, pp. 651-654.
"Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAM's" by Toru Kaga et al., IEEE Transactions on Electron Device, vol. 38, No. 2, Feb. 1991, pp. 255-261.
"A New Stacked Capacitor Cell with Thin Box Structured Storage Node", by S. Inoue et al., Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo, 1989 pp. 141-144.
IEEE Transactions on Electron Devices, vol. 38, No. 2, 1991, pp. 255-260, Crown Shaped Stacked-Capacitor Cell For 1.5-V Operation 64-Mb DRAM's, by Kaga et al.
IEDM 91, pp. 473-476, Spreaded-Vertical-Capacitor Cell (SVC) For Beyond 64MBIT DRAMs by Matsuo et al.

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