Method of making buried gate insulator field effect transistor

Details Method of making buried gate insulator field effect transistor Method of making buried gate insulator field effect transistor

1996-10-07

1998-01-06

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 21, 437 26, H01L 21786

Patent

active

057054126

ABSTRACT:
A buried, gate insulator field effect transistor is disclosed. It comprises source, drain, substrate, gate, and a gate insulator layer separating the gate from the source, drain and substrate; and a protective silicon dioxide covering layer. Windows are excised into this covering layer to allow electrical connection to the source, substrate, drain, and gate. The substrate and gate are vertically aligned in the resulting structure. The source, drain and gate are fabricated from a doped, semiconductor of one polarity while the substrate is fabricated from doped semiconductor of the opposite polarity. The gate insulator layer is fabricated by implanting an element or elements selected from Group V, VI or VII into the semiconductor to form a semiconductor-compound insulator. Methods of fabricating this device are also disclosed. In one embodiment the device is fabricated on an insulating base layer. The gate is formed next to the base. In a second embodiment, no base is used. The gate insulator is formed between the gate and substrate. In both cases the gate insulator is formed within the semiconductor in a buried and protected mode.

REFERENCES:
patent: 4317686 (1982-03-01), Anand et al.
patent: 4385937 (1983-05-01), Ohmura
patent: 5135885 (1992-08-01), Furukawa et al.

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