Method for fabricating a multiple well structure for providing m

Details Method for fabricating a multiple well structure for providing m Method for fabricating a multiple well structure for providing m

1994-04-29

1997-01-21

Fourson, George

Fishing, trapping, and vermin destroying

437 47, 437 60, 437919, H01L 2170, H01L 2700

Patent

active

055959253

ABSTRACT:
A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

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Syuso Fujii, et al., "Session 16: Dynamic RAMs FAM 16.6: A 45ns 16Mb DRAM with Triple-Well Structure", IEEE, 1989, pp. 248-249.
S. Yoshikawa, et al., "Process Technologies for a High Speed 16MDRAM with Trench Type Cell", Semiconductor Device Engineering Laboratory, Toshiba Corp., pp. 67-68 (date unknown).

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