Method and apparatus to maintain cache coherency in a multiproce

Details Method and apparatus to maintain cache coherency in a multiproce Method and apparatus to maintain cache coherency in a multiproce

1991-01-10

1993-07-13

Dixon, Joseph L.

Boots, shoes, and leggings

3642401, 36424341, 36424344, 36496432, 36496434, 364DIG1, G06F 1300

Patent

active

052281361

ABSTRACT:
A cache coherency mechanism enabling efficient and dynamic switching between the maintenance protocols of the invalidate and update types. The mechanism can reduce traffic on the shared bus and improve the system performance. Usually each processor repeatedly accesses a limited area of the memory within a short span of time. That area is referred to as a "working set" with respect to the processor. Each time a write operation occurs to shared data, each of the sharing processors determines whether or not the data belongs to its working set. If a sharing processor determines that the data belongs to its working set, then the cache consistency is maintained by the update type of procedure. Otherwise cache consistency is maintained via the invalidate type of procedure. In one embodiment the invention improves the system performance by utilizing the above mechanism for determining the working set in conjunction with a new cache protocol, ALL.sub.-- READ. A plurality of processors in a multiprocessor system using snoopy caches frequently share data or instruction code at one address. According to the ALL.sub.-- READ protocol when a processor causes a read miss for data or code at an address, other processors likely to use the data or code automatically read it into their caches. By using the working set determination mechanism, only data in the working set is applied with ALL.sub.-- READ. This invention thereby provides ALL.sub.-- READ efficiently, reduces bus traffic and improves the system performance.

REFERENCES:
patent: 3840862 (1974-10-01), Ready
patent: 3848234 (1974-11-01), MacDonald
patent: 3938097 (1976-02-01), Niguette, III
patent: 4392200 (1983-07-01), Arulpragasam et al.
patent: 4843542 (1989-06-01), Dashiell et al.
patent: 4959777 (1990-09-01), Holman, Jr.
patent: 5008813 (1991-04-01), Crane et al.
patent: 5025365 (1991-06-01), Mathur et al.
patent: 5056002 (1991-10-01), Watanabe

Affiliated with

Also associated with

Rating

Method and apparatus to maintain cache coherency in a multiproce does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus to maintain cache coherency in a multiproce, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus to maintain cache coherency in a multiproce will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2319407